1. Field of the Invention
The present invention relates to a bus arbitration apparatus and a bus arbitration method and in particular, relates to a bus arbitration apparatus and a bus arbitration method accessing directly to a memory connected on a system bus and enabling to use the system bus.
2. Description of the Related Art
A technology has been known from the past, relating to a bus arbitration apparatus configured so that a fluctuation of data transfer timing and a fluctuation of arbitration waiting time is absorbed by a FIFO (First In First Out) buffer, and a difference of the amount of the data transfer of each bus master and a difference of information related to the data transfer and so on are reflected to the arbitration, thereby preventing FIFO buffer from overflow/underflow.
For example, a bus arbitration apparatus is known which decides the priority of bus use in the order of sending a request of the bus use (data transfer request) to prevent the processing of each bus master from failing.
For example, Kokai (Japanese unexamined patent publication) No. H6(1994)-60017 proposes an arbitration circuit which gives an urgent bus acquisition signal in exceeding a predetermined time limit when during one bus master performs the data transfer the other bus master requests the data transfer, or an arbitration circuit which counts the cycle number that the bus master requests to decide the priority in order of requesting, as a bus arbitration apparatus suppressing overflow/underflow of the FIFO buffer.
As a result, a data transfer grant is given to the bus master requesting the data transfer later, and the FIFO buffer of the bus master does not fall into the overflow/underflow.
Kokai (Japanese unexamined patent publication) No. 2002-304367 proposes a round robin type arbiter having a tree structure for preventing of processing speed reduction even if number of bus master increases when arbitrating the requests of a plurality of bus masters.
According to a technology proposed in Kokai (Japanese unexamined patent publication) No. H6(1994)-60017, it becomes possible to improve the processing capability of the bus arbitration apparatus and to cut the FIFO buffer capacity that should be provided in each bus master, however, it may be not possible to judge whether or not the system fails.
For example, an arbitration circuit proposed in Kokai (Japanese unexamined patent publication) No. H6(1994)-60017 is configured so that an urgent bus acquisition signal is sent when exceeding a predetermined time limit and a data transfer grant is given in response to that, however, even if this urgent path is provided, when a plurality of bus masters exceed this time limit, it may be not possible to secure that the FIFO buffer falls into the overflow/underflow.
Further, even if the FIFO buffers of two or three bus masters are made not to fall into the overflow and so on at the same time by relaxing the time limit and giving the urgent bus acquisition signal, in consideration of increase of number of bus master due to becoming large of system in one chip and diversification of system modes in one chip in the recent years, more than two or three bus masters may fall into the overflow and so on at the same time.
When relaxing the time limit further, the urgent bus acquisition signal is generated more easily, as a result, the arbitration based on the urgent bus acquisition signal may be performed among all the bus masters. In this case, there may be no point in providing the urgent bus acquisition signal.